Makefile $<?

Hello,
I am reading this book: How Linux Works.
In chapter 15, Development tools, 15.2.6 Standard macros and variables, this little program concerning makefile is presented with very little precision:

.in.out: $<
myprog $< -o $*.out

I understood what ".SUFFIXES: .in" means
I understood what ".in.out:" means

In the recipe "myprog $< -o $*.out", $< corresponds to the first prerequisite of the rule (with a recipe).

However, I wonder about ".in.out: $<"
What does that mean exactly?

Thanks for your help.

My (limited) understanding is that:

1. .in.out: $< means that $< is a dependency / requirement for the .in.out (pseudo) target.
2. $< is a short cut for root root (left part) of the target. Meaning that a target of a.in.out will have a dependency of a.in.
3. Make will need to ensure that a.in is up to date before it can be used to build a.in.out.
4. The .in.out pseudo target is sort of akin to *.in.out in that it as a single entry can work with multiple files without needing to explicitly specify them.

I could be completely wrong. I'd have to refer to Make documentation which I don't have handy at the moment.

Thank's for your answer.

the GNU make (pdf)describes what .SUFFIXES means.

page 34 (4.8 Special Built-in Target Names):
.SUFFIXES
The prerequisites of the special target .SUFFIXES are the list of suffixes to be used in checking for suffix rules.

page 136 (10.7 Old-Fashioned Suffix Rules):
Suffix rules are the old-fashioned way of defining implicit rules for make. Suffix rules are obsolete because pattern rules are more general and clearer. They are supported in GNU make for compatibility with old makefiles. They come in two kinds: double-suffix and single-suffix.

A double-suffix rule is defined by a pair of suffixes: the target suffix and the source suffix. It matches any file whose name ends with the target suffix. The corresponding implicit prerequisite is made by replacing the target suffix with the source suffix in the file name. A two-suffix rule ‘.c.o’ (whose target and source suffixes are ‘.o’ and ‘.c’) is equivalent to the pattern rule ‘%.o : %.c’.

page 131:
$< The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule (see Chapter 10 [Implicit Rules], page 121).

Therefor I wonder why $< is in the prerequisites...

Otherwise I understand everything.

Thierry.

Sounds like your new information / quote is much closer than I am.

I'd have to reference what you wrote and more to be able to give a better answer.

Please share what you learn.

@thierry

According to the current-version "ultimate group-think AI chatbot" (ChatGPT 4o), GNU Make, $< is a special automatic variable that represents the first prerequisite in a rule. This variable is especially relevant for implicit rules, where the first prerequisite is typically the source file needed to produce the target. Let genAI clarify why $< appears in the recipe (not the prerequisites) of a rule and how it functions:

1. Implicit Rules and $< in Recipes

When Make uses implicit rules, like suffix or pattern rules, it automatically determines the prerequisites for the target. For example, with a suffix rule .c.o or a pattern rule %.o : %.c, Make knows that .c files are needed to produce .o files. The $< variable allows the rule to reference this source file (the first prerequisite) in the recipe for generating the target file.

For instance @thierry , consider the implicit rule for .o files:

%.o: %.c

$(CC) -c $< -o $@

Here:

• $< refers to the first prerequisite (the .c file).

• $@ refers to the target (the .o file).

Using $< in the recipe allows Make to compile .c files into .o files without needing to explicitly specify the .c file name each time, leveraging the implicit rule instead.

2. Why $< is Not in the Prerequisites

The prerequisites section (to the right of the colon) defines what files are needed before the target can be built, but $< itself is not listed there because it’s simply a placeholder for the first prerequisite. For instance:

myprogram: main.o utils.o

$(CC) $< -o $@

In this example, $< is not a prerequisite itself. Instead, it refers to the first prerequisite in the recipe, simplifying the rule so you don’t need to type the file name explicitly.

3. How Suffix and Pattern Rules Use $<

Suffix rules, like .c.o, automatically define the prerequisite file based on the suffix and the target. For .c.o, Make implicitly knows to look for a .c file to create the .o target. Using $< allows Make to reference this file within the recipe:

.c.o:

$(CC) -c $< -o $@

This way, if you have multiple .c files, Make will apply this rule to each one, using $< to refer to the respective .c file for each .o target.

In summary, according to genAI speak, $< is used within the recipe to dynamically reference the first prerequisite, making Makefiles more concise and adaptable by avoiding hardcoded filenames.