Use of commands of analyze and elaborate in design compiler

Hi I am trying to read a verilog code into the design compiler and I am using the following commands but I am getting an error.

analyze -format verilog -lib WORK dff_sync_reset.v
Error:   *** Presto compilation terminated with 1 errors. ***
elaborate dff_reset_sync -arch �verilog� -lib WORK

Error: Error: Can't find the architecture 'dff_reset_sync(verilog)' in the library 'WORK'
0

I am getting these errors so I think the file is not linked to UNIX. Can you please tell me if I am doing anything wrong.