[Solved] makefile conditions

Hi Everyone,

I'm trying to write a makefile that has two options. 1. A make all that shall believe it or not make everything and 2. a make without option.

I need to setup a few arrays differently, depending on the option choosen i.e. all or without.

My first try consisted of me creating a file "without"

e.g.

without:
touch without
make

then testing for that file using wildcard. I could not get this to work and it didnt even look like it was falling into the else condition.

So, attempt number two. I was thinking of creating a function similar to that of a shell script but from what i have read, this is not possible and i saw reference to something like this:-

without = \
@echo -e "Making Airsurf [Without PIF]"
VPATH = $(APP_C):$(IMS_C):$(COM_C)
CCP = g++ -Wall -O2 -DMENU -DCPU=I80386 -Wno-deprecated -Wno-write-strings -Wno-non-virtual-dtor -DUSEMYSQL -DUSESDL

then inside the actual rule:-

without:
$(call, without)

This also did not work, and variables never seemed to get set, or i would end up in an infinite loop.

Can anyone explain where i maybe going wrong or throw some ideas of what else may work my way? In theory this is a simple problem

if running make 1: set these variables else set variables to this instead.

Hope this post makes some sense

Thanks In Advance

The first rule a makefile encounters is the default rule. So have the first rule require everything, or require things which require everything.

I usually set up like this:

TARGETS=a bc def

all:$(TARGETS)

a:a.o

bc:b.o c.o

def:d.o e.o f.o

The all:$(TARGETS) rule forces it to build a bc def, which require all the fiddly little .o files, making it build everything.

A makefile which builds nothing by default would just have a do-nothing rule at the top I think:

TARGETS=a bc def

nothing:

all:$(TARGETS)

a:a.o

bc:b.o c.o

def:d.o e.o f.o

And you can choose the default rule at runtime, by the way! Anything the makefile's capable of making can be used. You could do anything from 'make nothing' to 'make all' to 'make c.o'. Don't think there's much need to make different makefiles for the purpose, just call make in different ways.

Helped me out alot

thanks,

Rob.