problem with Makefile

UNIX for Advanced & Expert Users
1

Hi,

I have a makefile which looks like this

ProcessA :
commands

touch pro1

ProcessB : pro1
commands

touch pro2

ProcessC: pro3
commands

and after some runs, i wish only pro3 to run and I check that "pro1" and "pro2" are there in the directory, but still, if i give make Process3, it starts right from ProcessA and does all the steps.
Is there anything wrong?

Thanks,
Balaji

2

There are several things to note, keep in mind that the make utility and makefiles are extremely versatile and can become extremely complicated.

I'll start at the beginning with some basics, if need be I can go into more detail later.

make does not need a makefile! If you have a file called prog.c you can type

3

Sorry, browser went funny ?

As I was saying, if you have a file called prog.c you can type
make prog
make has its own build in rules and will know how to create prog from prog.c

A simple makefile consists of targets and dependencies with associated commands, in general: -

target: dependency
<tab>command

I can't tell from your posting what whitespace you have in your makefile, this is important as the dependency line must NOT begin with a tab, the command line MUST begin with a tab.

I think there may be a couple of problems with your makefile, here's one that I believe will do what you want: -

ProcessA:
@echo "ProcessA"
touch proc1

ProcessB:
@echo "ProcessB"
touch proc2

ProcessC:
@echo "ProcessC"
touch proc3

You'll notice there are no dependencies, in fact there are NULL dependencies, this means the target is always rebuilt

you can now use
make ProcessA
make ProcessB
make ProcessC

however if you use make on its own it will only build the first dependency. This can be modified to build everything and can include more advanced techniques to selectively build different sources.

Let me know if you want more info, if so tell me what sources you are building with a little more detail, ie C/C++ files, related headers, etc.

Hope it helps.

4

qanta, if you have difficulty posting, you can edit your post. But also, I think you missed what he wants to do.

sskb, the crux of your problem is that you are using a rule named "ProcessA" to make a file called "pro1". You need to name the rule after the file that it will create. The name of a rule is called a "target" for a reason. You can use secondary rules to create "aliases" if you really want to. And, qanta has a point about the first rule. You should always tary to ensure that just using the command "make" will try to do the most useful thing.

Here is my makefile that I think addresses all of this. And as qanta points out, what I will type as spaces should be just a tab character.

default: ProcessC

ProcessA: pro1
ProcessB: pro2
ProcessC: pro3

pro1:
       @echo making pro1
       touch pro1

pro2: pro1
       @echo making pro2
       touch pro2

pro3: pro2
       @echo making pro3
       touch pro3