lom to ok prompt in netra 1280

UNIX Solaris
1

HI group,

Can anyone please suggest what can be the problem when we send poweron command on lom it again comes to lom and show following error
what does it means

lom>poweron
/N0/PS0: already on
/N0/PS1: already on
/N0/PS2: already on
/N0/PS3: already on
Powering boards on ...
Tue Dec 30 23:33:06 noname.example.com lom: Excluded unusable, unlicensed, faile
d or disabled board: /N0/IB6
Testing CPU Boards ...
Loading the test table from board SB0 PROM 0 ...
{/N0/SB0/P0} Running CPU POR and Set Clocks
{/N0/SB0/P1} Running CPU POR and Set Clocks
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Running CPU POR and Set Clocks
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Running CPU POR and Set Clocks
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P2} Running Basic CPU
{/N0/SB0/P3} Running Basic CPU
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P0} Running Basic CPU
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P1} Running Basic CPU
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P2} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P3} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P0} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P1} Subtest: Setting Fireplane Config Registers
{/N0/SB0/P2} Subtest: Display CPU Version, frequency
{/N0/SB0/P3} Subtest: Display CPU Version, frequency
{/N0/SB0/P0} Subtest: Display CPU Version, frequency
{/N0/SB0/P1} Subtest: Display CPU Version, frequency
{/N0/SB0/P2} Version register = 003e0015.b0000507
{/N0/SB0/P3} Version register = 003e0015.b0000507
{/N0/SB0/P0} Version register = 003e0015.b0000507
{/N0/SB0/P1} Version register = 003e0015.b0000507
{/N0/SB0/P2} Ecache Control Register 00000000.07c55400
{/N0/SB0/P3} Ecache Control Register 00000000.07c55400
{/N0/SB0/P0} Ecache Control Register 00000000.07c55400
{/N0/SB0/P1} Ecache Control Register 00000000.07c55400
{/N0/SB0/P2} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P3} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P0} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P1} Cpu/System ratio = 8, cpu actual frequency = 1200
{/N0/SB0/P2} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P3} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P0} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P1} @(#) lpost 5.18.1 2004/12/09 12:32
{/N0/SB0/P2} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P3} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P0} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P1} Copyright 2001-2004 Sun Microsystems, Inc. All rights reserved.
{/N0/SB0/P2} Use is subject to license terms.
{/N0/SB0/P3} Use is subject to license terms.
{/N0/SB0/P0} Use is subject to license terms.
{/N0/SB0/P1} Use is subject to license terms.
{/N0/SB0/P2} Subtest: I-Cache Initialization
{/N0/SB0/P3} Subtest: I-Cache Initialization
{/N0/SB0/P0} Subtest: I-Cache Initialization
{/N0/SB0/P1} Subtest: I-Cache Initialization
{/N0/SB0/P2} Subtest: D-Cache Initialization
{/N0/SB0/P3} Subtest: D-Cache Initialization
{/N0/SB0/P0} Subtest: D-Cache Initialization
{/N0/SB0/P1} Subtest: D-Cache Initialization
{/N0/SB0/P2} Subtest: W-Cache Initialization
{/N0/SB0/P3} Subtest: W-Cache Initialization
{/N0/SB0/P0} Subtest: W-Cache Initialization
{/N0/SB0/P1} Subtest: W-Cache Initialization
{/N0/SB0/P2} Subtest: P-Cache Initialization
{/N0/SB0/P3} Subtest: P-Cache Initialization
{/N0/SB0/P0} Subtest: P-Cache Initialization
{/N0/SB0/P1} Subtest: P-Cache Initialization
{/N0/SB0/P2} Subtest: Branch Prediction Initialization
{/N0/SB0/P3} Subtest: Branch Prediction Initialization
{/N0/SB0/P0} Subtest: Branch Prediction Initialization
{/N0/SB0/P1} Subtest: Branch Prediction Initialization
{/N0/SB0/P2} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P3} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P0} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P1} Subtest: E-Cache Global Variables Initialization
{/N0/SB0/P2} Subtest: Fast Init. Verification Test
{/N0/SB0/P3} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Subtest: Fast Init. Verification Test
{/N0/SB0/P1} Subtest: Fast Init. Verification Test
{/N0/SB0/P0} Running Enable MMU
{/N0/SB0/P1} Running Enable MMU
{/N0/SB0/P1} Subtest: IMMU Initialization
{/N0/SB0/P0} Subtest: IMMU Initialization
{/N0/SB0/P2} Running Enable MMU
{/N0/SB0/P3} Running Enable MMU
{/N0/SB0/P0} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: IMMU Initialization
{/N0/SB0/P1} Subtest: DMMU Initialization
{/N0/SB0/P3} Subtest: IMMU Initialization
{/N0/SB0/P2} Subtest: DMMU Initialization
{/N0/SB0/P3} Subtest: DMMU Initialization
{/N0/SB0/P2} Subtest: Map LPOST to local space
{/N0/SB0/P3} Subtest: Map LPOST to local space
{/N0/SB0/P2} Running FPU Tests
{/N0/SB0/P3} Running FPU Tests
{/N0/SB0/P0} Running FPU Tests
{/N0/SB0/P1} Running FPU Tests
{/N0/SB0/P0} Subtest: Map LPOST to local space
{/N0/SB0/P1} Subtest: Map LPOST to local space
{/N0/SB0/P0} Running Basic Ecache
{/N0/SB0/P1} Running Basic Ecache
{/N0/SB0/P0} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P2} Running Basic Ecache
{/N0/SB0/P1} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Running Basic Ecache
{/N0/SB0/P2} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P3} Subtest: E-Cache Initialization of first 1K
{/N0/SB0/P2} Subtest: E-Cache Initialization
{/N0/SB0/P0} Subtest: E-Cache Initialization
{/N0/SB0/P1} Subtest: E-Cache Initialization
{/N0/SB0/P3} Subtest: E-Cache Initialization
{/N0/SB0/P2} Running Memory Registers Tests
{/N0/SB0/P3} Running Memory Registers Tests
{/N0/SB0/P2} Subtest: Disable Memory Controllers
{/N0/SB0/P3} Subtest: Disable Memory Controllers
{/N0/SB0/P0} Running Memory Registers Tests
{/N0/SB0/P1} Running Memory Registers Tests
{/N0/SB0/P0} Subtest: Disable Memory Controllers
{/N0/SB0/P1} Subtest: Disable Memory Controllers
{/N0/SB0/P0} Running Memory Configuration Tests
{/N0/SB0/P1} Running Memory Configuration Tests
{/N0/SB0/P0} Subtest: Memory Controller Configuration
{/N0/SB0/P1} Subtest: Memory Controller Configuration
{/N0/SB0/P2} Running Memory Configuration Tests
{/N0/SB0/P3} Running Memory Configuration Tests
{/N0/SB0/P2} Subtest: Memory Controller Configuration
{/N0/SB0/P3} Subtest: Memory Controller Configuration
{/N0/SB0/P1} Subtest: UP Memory Clear
{/N0/SB0/P0} Subtest: UP Memory Clear
{/N0/SB0/P2} Subtest: UP Memory Clear
{/N0/SB0/P3} Subtest: UP Memory Clear
{/N0/SB0/P0} Running Memory Tests
{/N0/SB0/P1} Running Memory Tests
{/N0/SB0/P2} Running Memory Tests
{/N0/SB0/P3} Running Memory Tests
{/N0/SB0/P0} Running Advanced CPU Tests
{/N0/SB0/P1} Running Advanced CPU Tests
{/N0/SB0/P2} Running Advanced CPU Tests
{/N0/SB0/P3} Running Advanced CPU Tests
{/N0/SB0/P0} Running CPU ECC Tests
{/N0/SB0/P1} Running CPU ECC Tests
{/N0/SB0/P2} Running CPU ECC Tests
{/N0/SB0/P3} Running CPU ECC Tests
{/N0/SB0/P2} Running System Level Tests
{/N0/SB0/P3} Running System Level Tests
{/N0/SB0/P0} Running System Level Tests
{/N0/SB0/P1} Running System Level Tests
{/N0/SB0/P0} Running Board Memory Interleave
{/N0/SB0/P1} Running Board Memory Interleave
{/N0/SB0/P0} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P1} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P2} Running Board Memory Interleave
{/N0/SB0/P3} Running Board Memory Interleave
{/N0/SB0/P2} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P3} Subtest: Board Memory Interleave Configuration
{/N0/SB0/P0} Passed
{/N0/SB0/P1} Passed
{/N0/SB0/P2} Passed
{/N0/SB0/P3} Passed
Testing IO Boards ...
Tue Dec 30 23:33:56 noname.example.com lom: No usable Io board in domain.
lom>

Regards

Sameer

2

there is NO io board added to the domain. so you can't go to ok prom. post the output of "showboard -v" and lets have a look at the configuration.

3

Hi Dukenuke2

Thanks for the reply

I am writting down the reply of showboard as you asked

lom>showboard -v

Slot Pwr Component Type State Status
---- --- -------------- ----- ------
SSC1 On System Controller Main Passed
/N0/SCC - System Config Card Assigned OK
/N0/BP - Baseplane Assigned Passed
/N0/SIB - Indicator Board Assigned Passed
/N0/SPDB - System Power Distribution Bd. Assigned Passed
/N0/PS0 On D142 Power Supply - OK
/N0/PS1 On D142 Power Supply - OK
/N0/PS2 On D142 Power Supply - OK
/N0/PS3 On D142 Power Supply - OK
/N0/FT0 On Fan Tray Auto Speed Passed
/N0/RP0 On Repeater Board Assigned OK
/N0/RP2 On Repeater Board Assigned OK
/N0/SB0 On CPU Board Assigned Passed
SB2 - Empty Slot Assigned -
SB4 - Empty Slot Assigned -
/N0/IB6 On PCI I/O Board Assigned Disabled
/N0/MB - Media Bay Assigned Passed

Component J-No. Size Reason
--------- ----- ---- ------
/N0/SB0/P0/B0/D0 J13300 512 MB
/N0/SB0/P0/B0/D1 J13400 512 MB
/N0/SB0/P0/B0/D2 J13500 512 MB
/N0/SB0/P0/B0/D3 J13600 512 MB
/N0/SB0/P0/B1 - - DRAM DIMM Group 1 Empty
/N0/SB0/P1/B0/D0 J14300 512 MB
/N0/SB0/P1/B0/D1 J14400 512 MB
/N0/SB0/P1/B0/D2 J14500 512 MB
/N0/SB0/P1/B0/D3 J14600 512 MB
/N0/SB0/P1/B1 - - DRAM DIMM Group 1 Empty
/N0/SB0/P2/B0/D0 J15300 512 MB
/N0/SB0/P2/B0/D1 J15400 512 MB
/N0/SB0/P2/B0/D2 J15500 512 MB
/N0/SB0/P2/B0/D3 J15600 512 MB
/N0/SB0/P2/B1 - - DRAM DIMM Group 1 Empty
/N0/SB0/P3/B0/D0 J16300 512 MB
/N0/SB0/P3/B0/D1 J16400 512 MB
/N0/SB0/P3/B0/D2 J16500 512 MB
/N0/SB0/P3/B0/D3 J16600 512 MB
/N0/SB0/P3/B1 - - DRAM DIMM Group 1 Empty

Component Segment Compatible In Date Time Build Version
--------- ------- ---------- -- ---- ---- ----- -------
SSC1/FP0 - - - - - - RTOS version: 41
SSC1/FP1 ScApp Reference 12 12/09/2004 12:45 1.0 5.18.1
SSC1/FP1 Ver - - 12/09/2004 12:45 1.0 5.18.1 Build_01
/N0/IB6/FP0 iPOST Yes 12 12/09/2004 12:36 1.0 5.18.1
/N0/IB6/FP0 Ver - - 12/09/2004 12:45 1.0 5.18.1 Build_01
/N0/IB6/FP0 Info - 12 12/09/2004 12:37 1.0 5.18.1
/N0/SB0/FP0 POST Yes 12 12/09/2004 12:32 1.0 5.18.1
/N0/SB0/FP0 OBP Yes 12 12/09/2004 12:31 1.0 5.18.1
/N0/SB0/FP0 Ver - - 12/09/2004 12:40 1.0 5.18.1 Build_01
/N0/SB0/FP0 Info - 12 12/09/2004 12:33 1.0 5.18.1
/N0/SB0/FP1 POST Yes 12 12/09/2004 12:32 1.0 5.18.1
/N0/SB0/FP1 OBP Yes 12 12/09/2004 12:31 1.0 5.18.1
/N0/SB0/FP1 Ver - - 12/09/2004 12:40 1.0 5.18.1 Build_01
/N0/SB0/FP1 Info - 12 12/09/2004 12:33 1.0 5.18.1

Slot Populated Slot Description
---- --------- ----------------
/N0/IB6/P0/B1/C0 Empty 33MHz. 5V Short PCI card
/N0/IB6/P0/B1/C1 Empty 33MHz. 5V Short PCI card
/N0/IB6/P1/B1/C2 Empty 33MHz. 5V Short PCI card
/N0/IB6/P1/B1/C3 Empty 33MHz. 5V Short PCI card
/N0/IB6/P1/B1/C4 Empty 33MHz. 5V Short PCI card
/N0/IB6/P0/B0/C5 Empty 66/33MHz. 3.3V Short PCI card

Component Part # Serial # Description
--------- ------ -------- -----------
/N0/SB0 540-5467-03-51 A30201 CPU Board (1280)
/N0/SB0/P0/B0/D0 501-5030-03-50 K07DBJ 512 MB NG SDRAM DIMM
/N0/SB0/P0/B0/D1 501-5030-03-50 K076XY 512 MB NG SDRAM DIMM
/N0/SB0/P0/B0/D2 501-5030-03-50 K076XR 512 MB NG SDRAM DIMM
/N0/SB0/P0/B0/D3 501-5030-03-50 K076YB 512 MB NG SDRAM DIMM
/N0/SB0/P1/B0/D0 501-5030-03-50 K07DB6 512 MB NG SDRAM DIMM
/N0/SB0/P1/B0/D1 501-5030-03-50 K076XN 512 MB NG SDRAM DIMM
/N0/SB0/P1/B0/D2 501-5030-03-50 K07DB8 512 MB NG SDRAM DIMM
/N0/SB0/P1/B0/D3 501-5030-03-50 K07D9L 512 MB NG SDRAM DIMM
/N0/SB0/P2/B0/D0 501-5030-03-50 K07D9Q 512 MB NG SDRAM DIMM
/N0/SB0/P2/B0/D1 501-5030-03-50 K076XL 512 MB NG SDRAM DIMM
/N0/SB0/P2/B0/D2 501-5030-03-50 K076XT 512 MB NG SDRAM DIMM
/N0/SB0/P2/B0/D3 501-5030-03-50 K07D8V 512 MB NG SDRAM DIMM
/N0/SB0/P3/B0/D0 501-5030-03-50 K076Y3 512 MB NG SDRAM DIMM
/N0/SB0/P3/B0/D1 501-5030-03-50 K076Y4 512 MB NG SDRAM DIMM
/N0/SB0/P3/B0/D2 501-5030-03-50 K07DBH 512 MB NG SDRAM DIMM
/N0/SB0/P3/B0/D3 501-5030-03-50 K07DBG 512 MB NG SDRAM DIMM
/N0/SB0/P0/E0 370-4128-03-50 2BP995 4MB Ecache Module
/N0/SB0/P0/E1 370-4128-03-50 2BP98D 4MB Ecache Module
/N0/SB0/P1/E0 370-4128-03-50 2BNP68 4MB Ecache Module
/N0/SB0/P1/E1 370-4128-03-50 2BNP6E 4MB Ecache Module
/N0/SB0/P2/E0 370-4128-03-50 2BP8TK 4MB Ecache Module
/N0/SB0/P2/E1 370-4128-03-50 2BP99E 4MB Ecache Module
/N0/SB0/P3/E0 370-4128-03-50 2BP8TU 4MB Ecache Module
/N0/SB0/P3/E1 370-4128-03-50 2BP8TB 4MB Ecache Module
/N0/IB6 540-5564-05-51 D30356 IB_SSC Assembly (1280)

Component Cpu Mask Description
--------- -------- -----------
/N0/SB0/P0 6.0 UltraSPARC-III+, 1200MHz, 8M ECache
/N0/SB0/P1 6.0 UltraSPARC-III+, 1200MHz, 8M ECache
/N0/SB0/P2 6.0 UltraSPARC-III+, 1200MHz, 8M ECache
/N0/SB0/P3 6.0 UltraSPARC-III+, 1200MHz, 8M ECache

lom>
lom>

Regards
Sameer

4

your io board is in status "disabled". without an io board your domain won't come up to ok prompt. you have to check why the board is disabled. maybe you should open a call at sun service hotline...

5

Hi

Thanks for helping us

Regards
Sameer

6

Hello Everybody

I want to know how can I enable IO device component. In this case, how to remove component from the black list. I know that we can use " enablecomponent" command at lom prompt. Could anyone tell me what will be the syntax in above case to enable IO device.