https://cs334.cs.vassar.edu/slides/08_Paging_Smaller_Tables.pdf
Just found some cool information regarding this.
I could not understand multi-level paging that much although I understand in high level overview. I am studying for system performance tuning (OS+pVM+DB) and these are the part of curriculum. Anyone can explain this with a toy example? For example virtual address space of 4 bits
Assume
Virtual Page Number is 3 bits
offset is 1 bit
Assume single level paging,
Now, we get 8 pages in page table and each page contains 2 entries.
Now, we want to page the page table.
In this page table, the new address space is of 3 bits.
Now, say p1=2 bits
d1=1 bits
We'll have 4 entry page table with 2 addresses per entry.
Now to access:
Say, I want to access page number 7 offset 1
Firstly, I'd go to outer page table, but then, how'd I look for 7 because outer page table is just of 2 bytes?
I put this into homework because this is where it fits (if it does, kindly disallow if not allowed).