GNU make doesn't pick up changes

It's been a while since I had to write a Makefile, but I've managed to clobber this together:

SRC=module1.c module2.c
OBJS=$(SRC:%.c=%.o)
HDR=include1.h include2.h

CC=gcc
CFLAGS=-Wall -ggdb -D_XOPEN_SOURCE -I. -ansi

all: program

program: $(OBJS)
        $(CC) $(CFLAGS) -o $@ $(OBJS)

.o: $(@:%.o=%.c) $(HDR)
        $(CC) $(CFLAGS) -c $<

clean:
        rm -f program $(OBJS)

It works for the most part, except when a change in one of the includes happens, result in make telling me "nothing to do".

$ make
gcc -Wall -ggdb -D_XOPEN_SOURCE -I. -ansi   -c -o module1.o module1.c
gcc -Wall -ggdb -D_XOPEN_SOURCE -I. -ansi   -c -o module2.o module2.c
gcc -Wall -ggdb -D_XOPEN_SOURCE -I. -ansi -o program module1.o module2.o
$ touch include1.h
$ touch include2.h
$ make
make: Nothing to be done for `all'.
$ touch module1.c
$ make
gcc -Wall -ggdb -D_XOPEN_SOURCE -I. -ansi   -c -o module1.o module1.c
gcc -Wall -ggdb -D_XOPEN_SOURCE -I. -ansi -o program module1.o module2.o
$

Both include?.h files are used in both module?.c files. I probably screwed up the prerequisite part of the target definition, but for the love of the FSM, I can't find it.

All files reside on a ext3 LV, without any special time-keeping options altered.

Any help would be greatly appreciated.

I think it's that the target doesn't depend on the headers. So adding them:

program: $(OBJS) $(HDR)

Tried that. It rebuilds the program target, but the intermediary objects are still unchanged.

you are built executable previously and objects and ex file are ready in current dir.maybe therefore make does not anything.
if you try `make clean` and then try again make will be process.

secondly touch command just change to modify/access times if the file is there and make command process only `module1.c` because of make detects that `module1.c` s timestamps are newer and rebuild executable with this object file.

regards
ygemici