bash script to compile multiple .c files with some options

Shell Programming and Scripting
1

I'm trying to write a bash script and call it "compile" such that running it allows me to compile multiple files with the options "-help," "-backup," and "-clean". I've got the code for the options written, i just can't figure out how to read the input string and then translate that into option running.
NOTE options are supposed to be used in the order they are written and can be written in any order.

2

Why not just write a Makefile?

3 
#!/bin/bash

opt=$1
case $opt in
        -help)
                echo "compiler with -help..."
                ;;
        -backup)
                echo "compiler with -backup..."
                ;;
        -clean)
                echo "compiler with -clean..."
                ;;
        *)
                echo "Usage: $0 {-help|-backup|-clean}"
                exit
                ;;
esac
4

As pludi said, makefiles are great for this kind of job.
What you have is: to to create something, this otherthing must be done before.

A common place on source compilation is:
I need to build the executable, but first I need to build each individual object. Than I link all objects to produce an executable.

The beauty on Makefiles is that it "knowns" your source file has changed and build only that single file you need.

$ cat Makefile

PROJECT = MyProject
EXECUTABLE = MyProgram
SOURCE = file1.c file2.c file3.c
OBJECTS = file1.o file2.o file3.o
#This is an easier way to define OBJECTS:
#OBJECTS = $(OBJECTS:%.c=%.o)

help:
   echo Here is a help message

# Prior to "backup", make will run "clean".
backup: clean
   cd .. && tar czvf /backup/$(PROJECT).tar.gz $(PROJECT)

clean:
   rm -f $(OBJECTS) $(EXECUTABLE)

CFLAGS = -Wall -ggdb3 -DSOME_DEFINE=1
LDFLAGS = -L/usr/local/lib -lsomelibname

# All the magic is here

# This is your main target, which depends upon target "program",
# you executable file.

all: $(EXECUTABLE)

# To build "$(EXECUTABLE)", you first need to build all separeted object file,
# i.e., each of your .c file must produce a corresponding .o file
# The special variable $@ means "the target name". On this case, it is "$(EXECUTABLE)'s value"
# The special variable $^ means "all depend targets". On this case, it is $(OBJECTS)'s value

$(EXECUTABLE): $(OBJECTS)
   gcc $(LDFLAGS) $(CFLAGS) -o $@ $^

# This is where any .c file becomes .o file

%.o: %.c
   gcc $(CFLAGS) -c $^ -o $@

You can now run:

$ make all

if you update file2.c, make sees it's timestamp is newer than corresponding file2.o and recompiles it, then relinks it into your executable.

To cleanup all objects:

$ make clean

And so on...

$ make help
$ make backup

Nice, uh?

PS: That makefile was not tested, probably have some problems.

5

Perfect, thanks! I'm new to my command terminal, thanks for the Make tip

6

I'm 65 years old and I just started programming in C using Ubuntu for fun.
Very curious as to whether this could be done without using makefiles?
Is it possible.
Thanks