Not sure if this is the right forum but......
This is an article about the difficulties in the engineering of 14nM fabs and lower production techniques.
Semiconductor Engineering .:. Battling Fab Cycle Times
Enjoy...
That really is a great article, I think one of the ways Intel is going to work around this is multi process chips... so things that aren't as performance intensive are going to be made on older faster cheaper processes, or more optimized processes. So they can make IO optimized drivers for high speed ram interfaces, logic optimized areas for the CPU, and low cost peripheral areas. It is certainly interesting to see companies trying to cope with the limits they are running up against. As well as they can conentrate on making only one sub unit faster per generation... rather than thier tick - tock tock they have been doing. They could do some iteration on aspects of the design without having to worry about parts that won't change getting broken by moving to a new process etc.. .
I've seen some ideas about die stacking of CPU and GPU components instead of chips ram as is done with HBM. So, perhaps they would make tiny very high yeild dies, but stack a bunch of them and run them rather slowly for a higher aggregate speed so they don't fry themselves with heat.
As an aside I've actually seen Daifuku (Wynright is the specific branch I've worked with) equipment installed in several locations where I have been out on an on site setup trip for the equipment my employer makes... very cool cranes (I've seen them shuffling shoe boxes and potato chips) though apparently they shuffle computer chips around as well!