Remove some content from a verilog file

Shell Programming and Scripting
1

Hi,

I have a verilog file which looks like

module xyz (x, y, z, a, b, c);
input x;
input y;
input z;
output a;
output b;
output c;

initial begin
...
end

always ...
...

endmodule

What i want is to create a dummy of verilog module without the content so it should look like

module xyz (x, y, z, a, b, c);
input x;
input y;
input z;
output a;
output b;
output c;

endmodule

Any input is valuable. Thanks.

2

It looks like just matching input, output, module, and endmodule should catch all the relevant lines...

egrep "(input|output|module|endmodule)[ \t]" input > output
3

Corona688,

This does some of it. In the verilog file, the module definition could have

module xyz (
x,
y,
z,
a,
b,
c
);

instead of just

module xyz (x, y, z, a, b, c);

I need to capture the complete module where it ends with a ');'

4

What other things like that might slip it up? Show representative input and output, not idealized input and output.

5

Only the module can slip up. The input and output should be left as it is

module xyz (
x,
y,
z, a, b, c);

input x;
inputy;
output a;
output b;

endmodule
6

1) Turn all newlines into spaces, and semicolons into newlines. This will fix the line problem.
2) grep for the things you want.

tr '\n;' ' \n' <input | egrep "(input|output|module|endmodule)[ \t]" > output
7

nawk -f mat.awk myFile
mat.awk:

BEGIN {
  end=".*); *$"
}
/^module/ {
   if ($0 !~ end) {
    printf("%s", $0); m++
   }
   next
}
m {
   if ($0 ~ end)
     {print; m=0}
   else
     printf("%s", $0)
   next
}
1
8

This works great. Thanks Corona...