Makefile: multiple target variable substitution

Greetings!

Basically, I would like to properly handle this with gnu make:

alltools: my_tool mysecond_tool mythird_tool etc_tool

%_tool: dir1/%_tool.vf dir2/%_tool/subdir2/%_tool.ver
<tab>@echo done

%.vf:
<tab>RUN_VF $*

%.ver:
<tab>RUN_VER $*

So, if I were to do something like:
UNIX> make alltools

Where each _tool would be dependent on 2 files: dir1/_tool.vf & dir2/*_tool/subdir2/*_tool.ver.

However, it looks like make only allows one substitution per dependency. So what make actually tries to make are these files (for my_tool):
dir1/my_tool.vf & dir2/my_tool/subdir2/%_tool.ver

'my' did not get substituted into '%' at both places in the second dependency.

So, my question is, can this be done with some other special variable? Or, is there a simple trick to getting around this?

Thanks in advance!
Harlin!